by support »
The short, and most correct answer is: Because the standard says so.
The rationale behind this is that all bus accesses are done in DWs. If a bus entity needs to perform an operation at a smaller granularity, it is forced to use the Byte Enable bits, under pretty strict restrictions.
Think about the PCIe as an emulation for good old PCI: There were 32 physical data wires, physically connected to 32 data wires of some memory module. If the address wouldn't be DW aligned, there would be a need to route each of these data wires to four inputs of the memory module.
The short, and most correct answer is: Because the standard says so.
The rationale behind this is that all bus accesses are done in DWs. If a bus entity needs to perform an operation at a smaller granularity, it is forced to use the Byte Enable bits, under pretty strict restrictions.
Think about the PCIe as an emulation for good old PCI: There were 32 physical data wires, physically connected to 32 data wires of some memory module. If the address wouldn't be DW aligned, there would be a need to route each of these data wires to four inputs of the memory module.