The Xillybus Forum

Sharp!
I tried an update *((n32 *) ( this->iRegPciBase + regByteOff) + i ) = 0; and the issue has gone. Thanks a lot!

It looks like your issue is in C language, and not PCIe.

The question lies in the type of this->iRegPciBase. I suppose you want it to be a pointer to a 32-bit word, but you have something else, so the "+" operation isn't multiplied by 4. This results in successive unaligned 32-bit words. You wanted addr, addr+4, addr+8 etc. and got addr, addr+1, addr+2 instead.

Appreciate your time on my question:

I used a bus analyzer to capture PCIe traffic and found 32bit writes request each caused multiple transactions. This is a 4-lane PCIe system.
The bus analyzer is placed between CPU and PCIe switch.

The code used to do 32 bit writes ( running on the CPU, writing to peripheral FPGA at the other side of the PCIe switch) looks like

for(n32 i = 0 ; i < numOfWords ; i++)
{
*(n32 *) ( this->iRegPciBase + regByteOff + i ) = 0;
}

The analyzer captured
|32bit write|length 1|1st BE 1111|Data 00000000|Addr 60501D70|
|32bit write|length 2|1st BE 1110|last BE 0001|Data 41000000 00410041|Addr 60501D70|
|32bit write|length 2|1st BE 1100|last BE 0011|Data 41410000 00000041|Addr 60501D70|
|32bit write|length 2|1st BE 1000|last BE 0111|Data 41414100 00000041|Addr 60501D70|

I wonder if the issue is at the PCIe configurations or at the code compiler. Don't understand why write 0 to address 60501D70 triggers four transactions with a combinations of byte enables, and have length other than 1.
Ideally, it should only translate to one transaction with length 1, 1st BE 1111.