by support »
The question is if those packets were transmitted at all. Maybe something in the logic went wrong (for example, maybe the second packet was submitted to the FPGA logic before it was ready to accept it?).
I solve these situations with trying just random things: Inserting large delays between the packets (possibly writing to the same address), changing the address of the first packet, changing whatever. A few backs and forths, and the reason soon reveals itself. Once you have the first packet through, it's relatively easy to figure out why the next ones don't appear.
Good luck!
The question is if those packets were transmitted at all. Maybe something in the logic went wrong (for example, maybe the second packet was submitted to the FPGA logic before it was ready to accept it?).
I solve these situations with trying just random things: Inserting large delays between the packets (possibly writing to the same address), changing the address of the first packet, changing whatever. A few backs and forths, and the reason soon reveals itself. Once you have the first packet through, it's relatively easy to figure out why the next ones don't appear.
Good luck!