PCIe Addon board design queries

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Expand view Topic review: PCIe Addon board design queries

Re: PCIe Addon board design queries

Post by Guest » Fri Apr 13, 2018 3:41 am


Thanks for the clarification. Clears things up a bit !



Re: PCIe Addon board design queries

Post by support » Thu Apr 12, 2018 5:19 pm


The point of the PRSNT# pins is to give the receptor of the PCIe finger an indication of the physical size of the connector. For example, if a PCIe x 1 board is pushed into a x16 slot on the motherboard, the motherboard knows by virtue of the PRSNT# pins that it's only x1. It's just a short-circuit on the PCIe board, and has nothing to do with the FPGA.

This is not to be confused with PERST# which is a reset signal, which is how the motherboard resets the PCIe board.

As for WAKE#, this allows the FPGA to wake up the host from suspend. Not used by Xillybus at all (and I doubt any other FPGA application uses it).


PCIe Addon board design queries

Post by Guest » Thu Apr 12, 2018 6:08 am

Hi Eli,

I'm in the process of designing a Artix 7 based board with x1 PCIe. I went through the schematics of a few artix 7 boards, where they have tied the PCIE_PRSNT#1 and PCIE_PRSNT#2 signals together, and in some cases where there is a 4 lane, there is a jumper to select between 1x and 4x which is tied to the PCIE_PRSNT#1 on the top.

While I have previously used ML505, in that board, the same signal is connected via a NMOS to a FPGA pin.

Why is there this difference ? Has it got to do with the electromechanical specs of PCIe (I'm not able to get these documents !)

Which one should I follow ? I plan on using xillybus, and from previous experience, xillybus requires only PCIE_PERST, the clocks and the data pins.

Also, What are the consequences of not using the WAKE# ? Does it just block my ability to use hot-plugging/swapping ? I also see that most boards of xilinx with pcie effectively leave the wake signal open.

I would be grateful for any clarification !

Thanks !