by support »
Hi,
Well, the input to the transaction layer is TLPs. How to send them or receive them is a question of the FPGA family (or ASIC library) you're working with. For example, Xilinx present an AXI-stream interface, Altera use their Avalon interface. But in the end of the day, the application logic creates or dissects TLPs.
I hope this helped somehow.
Eli
Hi,
Well, the input to the transaction layer is TLPs. How to send them or receive them is a question of the FPGA family (or ASIC library) you're working with. For example, Xilinx present an AXI-stream interface, Altera use their Avalon interface. But in the end of the day, the application logic creates or dissects TLPs.
I hope this helped somehow.
Eli