by support »
Hello,
I assume that you refer to bus_clk (and not the clock on the PCIe hardware bus itself).
Xillybus exposes Xilinx' PCIe block's "application clock", which is the clock used for interfacing with the block, as bus_clk. You may hence change it by setting that block's lane and speed settings, as described in the Getting Started guide for Xilinx.
The demo bundle for Virtex-7 has a 250 MHz bus_clk, which is the maximal clock possible. You probably wouldn't benefit from a clock with a higher frequency, as it's getting non-trivial to meet timing.
If you want your own application logic to work with a different clock, use dual-clock FIFOs to interface with Xillybus, so that the side facing Xillybus is clocked with bus_clk, and the one facing your logic is clocked with whatever clock you chose.
Regards,
Eli
Hello,
I assume that you refer to bus_clk (and not the clock on the PCIe hardware bus itself).
Xillybus exposes Xilinx' PCIe block's "application clock", which is the clock used for interfacing with the block, as bus_clk. You may hence change it by setting that block's lane and speed settings, as described in the Getting Started guide for Xilinx.
The demo bundle for Virtex-7 has a 250 MHz bus_clk, which is the maximal clock possible. You probably wouldn't benefit from a clock with a higher frequency, as it's getting non-trivial to meet timing.
If you want your own application logic to work with a different clock, use dual-clock FIFOs to interface with Xillybus, so that the side facing Xillybus is clocked with bus_clk, and the one facing your logic is clocked with whatever clock you chose.
Regards,
Eli