by support »
Hello,
Looping back is perfectly fine with Xillybus IP core. You seem to refer to the guideline not to loop back in bandwidth
tests:
http://xillybus.com/doc/bandwidth-guidelinesWhen just looping back in the FPGA, Xillybus' IP core both fills and empties the FIFO in the middle very rapidly. There is however a latency between the moment a data transaction is possible to when it's carried out, which leads to a very uneven data transport. This, in turn, yields suboptimal bandwidth performance.
As this is a very artificial test case, the core isn't optimized to handle it better. It therefore makes no sense to test it for bandwidth this way.
Regards,
Eli
Hello,
Looping back is perfectly fine with Xillybus IP core. You seem to refer to the guideline not to loop back in bandwidth [b]tests[/b]:
http://xillybus.com/doc/bandwidth-guidelines
When just looping back in the FPGA, Xillybus' IP core both fills and empties the FIFO in the middle very rapidly. There is however a latency between the moment a data transaction is possible to when it's carried out, which leads to a very uneven data transport. This, in turn, yields suboptimal bandwidth performance.
As this is a very artificial test case, the core isn't optimized to handle it better. It therefore makes no sense to test it for bandwidth this way.
Regards,
Eli