by support »
Hello,
Your setup isn't completely clear, but I take it that the non-Intel CPU presents itself as a PCIe device on the bus. In that case, it has a PCI configuration space, in which the root complex (the bus root, the Intel CPU I guess) sets up the MSI feature during enumeration, if the device declares that MSI is activated.
More precisely, if the device presents a MSI capability by virtue of its configuration space, the bus enumerator (root complex) writes an address and data value to the device's configuration space. The device triggers an interrupt at the root complex by writing that value to that address. It's that simple, actually.
I hope this rather vague answer gave a direction.
Regards,
Eli
Hello,
Your setup isn't completely clear, but I take it that the non-Intel CPU presents itself as a PCIe device on the bus. In that case, it has a PCI configuration space, in which the root complex (the bus root, the Intel CPU I guess) sets up the MSI feature during enumeration, if the device declares that MSI is activated.
More precisely, if the device presents a MSI capability by virtue of its configuration space, the bus enumerator (root complex) writes an address and data value to the device's configuration space. The device triggers an interrupt at the root complex by writing that value to that address. It's that simple, actually.
I hope this rather vague answer gave a direction.
Regards,
Eli