by support »
Hi,
There is no specification on how the peripheral knows the addresses it can write to. But the common (well, probably only) way it's done is that the host informs the peripheral's logic about the bus address range it's allowed to write to by writing to registers in the endpoint's BAR space. How exactly is implementation specific.
And yes, in practice, any endpoint can write to any address on the bus (including to the BAR addresses of other endpoints for peer-to-peer communication). Relatively recent memory controllers have a unit called IOMMU, which translates and possibly denies access to certain memory regions, but these are usually not activated on common desktop computer. So yes, a faulty endpoint can easily trash the entire system.
Eli
Hi,
There is no specification on how the peripheral knows the addresses it can write to. But the common (well, probably only) way it's done is that the host informs the peripheral's logic about the bus address range it's allowed to write to by writing to registers in the endpoint's BAR space. How exactly is implementation specific.
And yes, in practice, any endpoint can write to any address on the bus (including to the BAR addresses of other endpoints for peer-to-peer communication). Relatively recent memory controllers have a unit called IOMMU, which translates and possibly denies access to certain memory regions, but these are usually not activated on common desktop computer. So yes, a faulty endpoint can easily trash the entire system.
Eli