DMA from FPGA to Host

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Re: DMA from FPGA to Host

Post by Guest »

Eli,

I just could run the hello world example on my platform. Just a few pin assignment and bam... it works. You have no idea how grateful I am. God bless you. This project is wonderful.

Best wishes for you

Re: DMA from FPGA to Host

Post by support »

I suggest starting from a fresh pcie_c4_1x.v, and open it with IP Compiler for PCI Express 13.0. There is no place for mystery here. It just worked for me.

Eli

Re: DMA from FPGA to Host

Post by Guest »

I think I just did it by editing the file and changing the name of megafunction to "IP Compiler for PCI Express v13.0" in the first line. I will keep you posted about how it works on my platform. :)

Thanks again

Re: DMA from FPGA to Host

Post by Guest »

Sorry, I didn't realize you updated that answer.

In the instruction, it says I should choose "Edit an existing custom megafunction variation". When you choose "Edit ..." the you can only pick up a file and picking pcie_c4_1x.v throws the error. I can pick "IP Compiler for PCI Express" if you choose to create a new megafunction, and then I have to enter all the parameters. I am not sure what you mean by picking "IP Compiler for PCI Express", because there is no option for that in edit.

P.S. I tried to edit the megafunction name inside the file and it didn't work either.

Re: DMA from FPGA to Host

Post by support »

It will work with Quartus 12.0. But didn't my answer above help?

Re: DMA from FPGA to Host

Post by Guest »

Thanks Eli,

It was really helpful. I would appreciate if you tell me how to fix the problem with Quartus. Would it work if I install an older version?

Re: DMA from FPGA to Host

Post by support »

Hi,

Apparently, you're using the Avalon-MM interface, which I'm not familiar with, so I'm afraid I can't help you much with this,

Eli

Re: DMA from FPGA to Host

Post by Guest »

Thanks again,

I want to ask a question about my implementation if it's fine. I have read the Altera PCIe IP Compiler documentation to understand how the translation table works. I have configured the IP Compiler to use dynamic address translation; In my device driver, I use dma_alloc_coherent function to get a memory region as DMA buffer, then I write dma_handle (bus address) of this region to the translation table of the device (I think I do this part correctly, so I skip the details). I initialize the memory in kernel, then send a signal to invoke the device, the device writes something to the TXS of PCIe IP Compiler using an Avalon MM Master interface. According to the docs, this write operation should be translated to a PCIe write packet. But after the handshakes are done, I don't see the right values in the memory. I see the same values I initialized in the kernel!

Please tell me if I'm missing something in this scenario. I have double-checked everything. I'm not an expert in device drivers. Maybe I have missed something there? Are there any necessary steps to grant DMA access, other than allocating the memory and sending the pointer over? That's my best guess.

Thanks

Re: DMA from FPGA to Host

Post by support »

Hi,

The answer was yes -- DMA is possible. PCIe is completely pointless without DMA.

As for the issue with Quartus, it expects you to pick "IP Compiler for PCI Express" (for Cyclone V it would have been "Cyclone V Hard IP for PCI Express 13.0"). This used to be set up automatically in Quartus 12.0.

Best regards,
Eli

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