by support »
Hello,
It depends on what you're working on. If you're doing the rock-bottom level interface for a PCIe link, it's possible that the bits in a single "popped" word will belong to different words as were sent from the transmitter, if the skew between the lanes exceeds the symbol clock rate. In that case, there's a need to fix this with some logic circuitry. For example, in a 5 GT/s link, a skew of 0.2 ns is enough to require deskewing logic.
On the other hand, if you're working with a PCIe core from some hardware vendor, you don't need to worry about this at all. This deskewing has been done for you.
Regards,
Eli
Hello,
It depends on what you're working on. If you're doing the rock-bottom level interface for a PCIe link, it's possible that the bits in a single "popped" word will belong to different words as were sent from the transmitter, if the skew between the lanes exceeds the symbol clock rate. In that case, there's a need to fix this with some logic circuitry. For example, in a 5 GT/s link, a skew of 0.2 ns is enough to require deskewing logic.
On the other hand, if you're working with a PCIe core from some hardware vendor, you don't need to worry about this at all. This deskewing has been done for you.
Regards,
Eli