by support »
Hello,
It's not exactly clear how you've set up your system, but apparently the write operations are driven by software. This means that each time you issue a write, a TLP with no more than 4 our 8 bytes is created, so you get a very low efficiency. On the face of it, it looks like the PCIe/AXI bridge is your bottleneck, as it probably handles TLP packets at a constant rate, no matter the lane with. Just a wild guess.
So yes, DMA is probably what you need there.
Anyhow, all TLP packets are sent on all lanes, so adding lanes does speed up the transmission of the data on the PCIe bus.
As for the TLP sniffing -- I simply connected the 32-bit wide TLP data wires of the PCIe block to a FIFO, and attached the other end to a Xillybus stream. The transmission of the data to the host created even more TLP data to sniff, but that's not necessarily a bad thing...
Regards,
Eli
Hello,
It's not exactly clear how you've set up your system, but apparently the write operations are driven by software. This means that each time you issue a write, a TLP with no more than 4 our 8 bytes is created, so you get a very low efficiency. On the face of it, it looks like the PCIe/AXI bridge is your bottleneck, as it probably handles TLP packets at a constant rate, no matter the lane with. Just a wild guess.
So yes, DMA is probably what you need there.
Anyhow, all TLP packets are sent on all lanes, so adding lanes does speed up the transmission of the data on the PCIe bus.
As for the TLP sniffing -- I simply connected the 32-bit wide TLP data wires of the PCIe block to a FIFO, and attached the other end to a Xillybus stream. The transmission of the data to the host created even more TLP data to sniff, but that's not necessarily a bad thing...
Regards,
Eli