The Xillybus Forum

Hi

I am not sure which Altera Core you were referring to, however the core I ran seemed to give me the proper Link Number (8'h01) in the Linkwidth_Accept LTSSM state and in the Lanenum_Accept state since I used just 1 lane I got 8'h00 as the lane number. This is for the Altera PHY IP Core for PCIe v13.1(1 lane 2.5GT/s).

Hello,

I'm sorry, but as of today, I haven't touched the low-level negotiation, so I can't help you much. Maybe someone else shows up with an answer...?

Eli

Hi Eli,

I'm studying the LTSSM and thinking to write a piece of code for this.
I'm confused with the Link and Lane Width Negotiation Part.

I understand that PAD will be used in the link and lane fields in TS1 ordered-set before the Link and Lane Width negotiating state. This is expected!
But during the the link and lane width negotiating state, I found that this 2 fields are always appear to be 8'h00 regardless of x8 or x4 configuration in the ALTERA PCIe example design...I double check the both TX transmitted data and RX received data, both always show 8'h00. (This means the INTEL CPU also sending 00 value of the link and lane field which is encapsulate inside the TS1 ordered set.)...

May I know why?
My expectation to this is I will see 8'h01 in the link field (Because only 1 link in being used), then for the lane field, I will see 8'h4 if my configuration is x4 or i will see 8'h8 if my configuration is x8....but none of this occur throughout the entire Link up process.

Please correct me if I'm wrong.

Thanks and Regards,