by Guest »
CPU MWR to the FPGA bar space, write the address range 0x00001400-0x00001800 (these addresses will be recycled, used from the 0x00001400, to the end of 0x00001800, and then used from the 0x00001400, polling), used only by 4 bytes to come, such as 1400 1404 1408 140c. for example, to add 1400, 1408, 1404 writes three data when running after a period of time, there was a shortage of frames or same frame, such as the following 3 frames the CPU: 400000010000000F 3010140000000001,400000010000000F 3010140400000002,400000010000000F 3010140800000002, FPGA end can only receive one of these three frames, Or two , that will lose one or two, sometimes it will receive two duplicate frames, but print information from the CPU test memory write operation is normal, so I do not know why this is so.
CPU MWR to the FPGA bar space, write the address range 0x00001400-0x00001800 (these addresses will be recycled, used from the 0x00001400, to the end of 0x00001800, and then used from the 0x00001400, polling), used only by 4 bytes to come, such as 1400 1404 1408 140c. for example, to add 1400, 1408, 1404 writes three data when running after a period of time, there was a shortage of frames or same frame, such as the following 3 frames the CPU: 400000010000000F 3010140000000001,400000010000000F 3010140400000002,400000010000000F 3010140800000002, FPGA end can only receive one of these three frames, Or two , that will lose one or two, sometimes it will receive two duplicate frames, but print information from the CPU test memory write operation is normal, so I do not know why this is so.