by support »
I have to admit that the atomic operations are beyond the scope of anything I'm doing, so I'm not so familiar with that.
And yes, it's true that the spec doesn't say anything about what happens in the data payload region, since it obviously doesn't care about its content. So the endpoint may reverse the bytes of the data payload (in fact, Altera's PCIe core in its Avalon-ST interface does that) and in that case bit 0 of Byte Enables will indeed correspond to bits [7:0].
We agree: There is no doubt that the endpoint logic is allowed to do whatever it wants when interfacing with the application logic. But if the endpoint just feeds the TLP through as it arrives from the data link layer with no specific manipulations, and it does so in 32 bit words, so that the bit field maps in the spec for the headers apply, then byte 0 is at [31:24], and bit 0 of BE corresponds to those bits. That's big Endian.
I have to admit that the atomic operations are beyond the scope of anything I'm doing, so I'm not so familiar with that.
And yes, it's true that the spec doesn't say anything about what happens in the data payload region, since it obviously doesn't care about its content. So the endpoint may reverse the bytes of the data payload (in fact, Altera's PCIe core in its Avalon-ST interface does that) and in that case bit 0 of Byte Enables will indeed correspond to bits [7:0].
We agree: There is no doubt that the endpoint logic is allowed to do whatever it wants when interfacing with the application logic. But if the endpoint just feeds the TLP through as it arrives from the data link layer with no specific manipulations, and it does so in 32 bit words, so that the bit field maps in the spec for the headers apply, then byte 0 is at [31:24], and bit 0 of BE corresponds to those bits. That's big Endian.