by mugundhan »
Hello Again Eli,
I modified the xillycapture module added a counter at 100 MHz, filling in a fifo and trying to transmit about 8192 4 byte counts. From the xillybus interface, I connected the read_32 fifo_rd_en signals, bus clock as the read enable and read clock for these signals. I have my own write logic, so I left the write_32 signals on the xillybus floating as I don't need them now. I also did the same for read_8 signals, where I have a 8 bit wide 64 byte deep fifo, where I only write, so I left the read signals floating. Is this ok ? or must these signals need be asserted to 0 or Vdd ?
Sorry for asking a very trivial question, but didn't want to progress without clarification ^_^ .
thank you !
Hello Again Eli,
I modified the xillycapture module added a counter at 100 MHz, filling in a fifo and trying to transmit about 8192 4 byte counts. From the xillybus interface, I connected the read_32 fifo_rd_en signals, bus clock as the read enable and read clock for these signals. I have my own write logic, so I left the write_32 signals on the xillybus floating as I don't need them now. I also did the same for read_8 signals, where I have a 8 bit wide 64 byte deep fifo, where I only write, so I left the read signals floating. Is this ok ? or must these signals need be asserted to 0 or Vdd ?
Sorry for asking a very trivial question, but didn't want to progress without clarification ^_^ .
thank you !