No response from FPGA. Aborting

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Expand view Topic review: No response from FPGA. Aborting

Re: No response from FPGA. Aborting

Post by Tariq » Wed Feb 12, 2020 1:18 pm

During the kernel loading processing, it gives the similar report a debug message :"xillybus_of 50000000.xillybus: No response from FPGA. Aborting."
The deice tree built for xillybus is as follows:
xillybus_ip@50000000 {
compatible = "xillybus,xillybus-1.00.a";
interrupt-names = "Interrupt";
interrupt-parent = <0x4>;
interrupts = <0x0 0x3a 0x4>;
reg = <0x50000000 0x1000>;
xlnx,dphase-timeout = <0x8>;
xlnx,max-burst-len = <0x100>;
xlnx,native-data-width = <0x40>;
xlnx,s-axi-min-size = <0x1ff>;
xlnx,slv-awidth = <0x20>;
xlnx,slv-dwidth = <0x40>;
xlnx,use-wstrb = <0x1>;
dma-coherent;
};

How did you solve this problem?

Re: No response from FPGA. Aborting

Post by jeasinema » Sat Sep 24, 2016 7:16 am

Thanks for your reply!

Re: No response from FPGA. Aborting

Post by support » Sat Sep 24, 2016 7:04 am

Hello,

Non-coherent DMA means that the processor's cache may or may not be coherent with the physical RAM, so special cache synchronization commands are required before the processor accesses memory regions written to by DMA, or after writing to memory regions before they're read from with DMA.

Coherent DMA means that the cache is kept in sync by the processor's infrastructure as DMA operations take place.

x86/x86_64 architectures are always cache coherent. As for Zynq, only the ACP port enforces cache coherency.

Since Xillybus is attached to the ARM's ACP port in Xillinux, cache coherency is ensured, and hence the dma-coherent option in the device tree. If you remove that option, the driver will issue these cache synchronization commands, which mess up things and cause the initialization to fail.

Regards,
Eli

Re: No response from FPGA. Aborting

Post by Guest » Sat Sep 24, 2016 6:41 am

Hi, Eli

I've read this doc about xillybus and devidetree: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/Documentation/devicetree/bindings/xillybus/xillybus.txt. And I got a question with this:

Optional properties:
- dma-coherent: Present if DMA operations are coherent


What is "DMA operations are coherent"? I use xillybus with Xilinx-Zynq7020, If I remove this line, xillybus would not be detected by kernel, with "No response from FPGA. Aborting".

Thanks!

Re: No response from FPGA. Aborting

Post by jeasinema » Fri Sep 23, 2016 5:31 am

Hi, Eli

I just solved this problem by setting the accurate interrupt number for xillybus in devicetree.(follow this tutorial http://xillybus.com/tutorials/device-tree-zynq-4) It seems that there are more items need to be modified in the devicetree file generated by the vivado SDK built-in generator.

Sorry for disturbance.

Re: No response from FPGA. Aborting

Post by support » Thu Sep 22, 2016 4:59 pm

Hello,

The error message means that the driver failed to initialize the Xillybus logic. More specifically, the logic didn't issue an interrupt at some point in the initialization, in which it's expected to do so. Since it doesn't talk with us, it's a bit difficult to figure out exactly what's wrong.

Since you've apparently modified the processor's settings (or else why would you rebuild boot.bin), there can be countless reasons for this failure. I suggest trying to isolate the change that broke things by starting from the original setting, and gradually changing parameters. I hope this makes sense.

Regards,
Eli

No response from FPGA. Aborting

Post by jeasinema » Thu Sep 22, 2016 3:45 pm

I've got some problem with xillybus, and here are the descriptions:
1. During the kernel loading processing, it report a debug message :"xillybus_of 50000000.xillybus: No response from FPGA. Aborting."
2. Xilinux boots successfully, but I cannot find the xillybus devices in /dev/.

Some infos which may be useful:
1. I use Xilliux-1,3 with a zedboard-like Zynq-7020 board.
2. I use a vivado project generated by a Tcl script in xillinux-eval-zedboard-1.3c.zip(verilog version)
3. I've made some essential modifications in the project, then generated a bitstream and fsbl.elf
4. I rebuilt u-boot, then generate boot.bin with fsbl.elf built at 3
5. I built devicetree using this tutorial:http://www.wiki.xilinx.com/Build+Device+Tree+Blob, here is the part about xillybus:
Code: Select all
   
amba_pl {
      #address-cells = <0x1>;
      #size-cells = <0x1>;
      compatible = "simple-bus";
      ranges;

      xillybus@50000000 {
         compatible = "xillybus,xillybus-1.00.a";
         interrupt-parent = <0x3>;
         interrupts = <0x0 0x1e 0x4>;
         reg = <0x50000000 0x1000>;
         xlnx,dphase-timeout = <0x8>;
         xlnx,max-burst-len = <0x100>;
         xlnx,native-data-width = <0x40>;
         xlnx,s-axi-min-size = <0x1ff>;
         xlnx,slv-awidth = <0x20>;
         xlnx,slv-dwidth = <0x40>;
         xlnx,use-wstrb = <0x1>;
         dma-coherent;
      };

      xillybus_lite@50002000 {
         compatible = "xillybus,xillybus_lite_of-1.00.a";
         interrupt-parent = <0x3>;
         interrupts = <0x0 0x1d 0x1>;
         reg = <0x50002000 0x1000>;
      };

      xillyvga@50001000 {
         compatible = "xlnx,xillyvga-1.0";
         reg = <0x50001000 0x1000>;
         xlnx,dphase-timeout = <0x8>;
         xlnx,max-burst-len = <0x10>;
         xlnx,native-data-width = <0x20>;
         xlnx,s-axi-min-size = <0x1ff>;
         xlnx,slv-awidth = <0x20>;
         xlnx,slv-dwidth = <0x20>;
         xlnx,use-wstrb = <0x1>;
      };
   };

Thanks in advance!

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