The Xillybus Forum

Hello,

Oh !

Thank you for the clarification

Mugundhan

Hello,

In theory, you should rmmod the xillybus_pcie kernel module, reprogram the FPGA and rescan the bus, which should cause the module to reload and initialize the updated Xillybus IP core on the FPGA.

The problem is the rescanning. As far as I know, there is no way to rescan the PCI/PCIe bus on Linux (in Windows it's possible), even despite the

echo 1 > /sys/bus/pci/rescan

command suggested all over the web. For all I know, it simply doesn't work. Maybe because there are many active devices that would be affected (graphics card in particular).

So unless you have better luck with the rescanning, the answer is no -- a reboot it required.

Regards,
Eli

Hello Eli,

Currently, when I reprogram the FPGA with a new bit file containing xillybus attached to the main logic, I restart the system manually. If I don't, I get the device or resource busy error. Is there a way where I can refresh my device files on the host everytime I reprogram the FPGA without rebooting the system ?

Kindly Advice,

Mugundhan