FPGA gives a "unknown header type 7f" with lspci command

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Expand view Topic review: FPGA gives a "unknown header type 7f" with lspci command

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by support »

Just a small piece of information, that doesn't necessarily help with the original problem:

"Unknown header type 7f" seems to be the result of a no-response from the FPGA to the host's request of the configuration register information. So the situation is probably that the FPGA was enumerated properly, but then stopped to respond later, or didn't respond properly. Maybe it was in a low-power state and didn't wake up properly, or some other kind of mishap.

So there's a whole variety of reasons for this to happen.

Eli

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by Guest »

Ok, after a few days of trial and error, I've managed to solve the problem!

In section 4.5.3 of the document pointed by Eli, it states: "the PCIE_LANE parameter in xillybus.v is larger than the example design’s, there is
no problem leaving it that way, and it’s often easier to do so". This is not true!

I had to modify the PCIE_LANE parameter in xillybus_block.v in the demo bundle and regenerate the Vivado project using xillydemo-vivado.tcl

Works like a charm after that :)

Thanks Eli for pointing me in the right direction! I would suggest modifying that section of the document.

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by support »

Hello,

The error you report occurs before Xillybus' logic gets a say: The lspci detection is a matter between Xilinx' PCIe block and the operating system. Therefore, the problem lies somewhere in the region of the IP core itself and the timing constraints. I can't see anywhere else where it would hide.

The fact that you've taken the PCIe block and generated an example project from it, and that went fine, doesn't leave a lot of room. Just to be sure, please diff the XCI files of the PCIe block in the bundle and that in the example project that worked. I would expect them to be identical, except for the name of the IP. If not, what are the differences?

You mentioned using the constraints from the example project directly, and that it didn't work. Well, it shouldn't. Note that section 4.5.4 in the said Getting started guide doesn't tell you to copy the constraints, but you're supposed to adapt them, editing the paths to the signals. Maybe you missed this little delicate point?

Regards,
Eli

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by Guest »

Hi Eli,

I've verified that Vivado consumed the timing constraints correctly. I've even used the timing constraints from the working Vivado example project on the Xillybus bundle project to no avail - no problem for Gen1 but gives "unknown header type 7f" for Gen2.

Do you have any other suggestions?

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by Guest »

Hi Eli,

Ok thank you, I will try to update the timing constraints.

Yes, for the Xilinx's example project I generated it from the PCIe block in the Xillybus bundle.

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by support »

Hello,

It sounds like you didn't update the timing constraints correctly. If you did, please verify that Vivado is actually consuming the timing constraint file you edited (e.g. by deliberately making an error in it).

As for comparing with Xilinx' example project: Did you try the example project that is generated from the PCIe block in the Xillybus bundle, or some project provided by Xilinx as something to download and run? If the latter, definitely try the former.

Regards,
Eli

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by Guest »

Hi,

Ok thanks for your reply. I've implemented the recommendations in section 4.5 and section 5.0 of the document.
However, I still cannot get the bundle design to work for Gen2 (5.0GT/s).

I've also tried the example design from Xilinx and my PC successfully enumerated the FPGA device as Gen2 with no "unknown header type 7f" problem.

Is there something else that I'm missing?

Thanks

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by support »

Hello,

The bundles are set up with the lowest link speed that matches the IP core's capabilities. As each Gen1 lane gives approximately 200 MB/s, and a rev B IP core is limited to 1600 MB/s, there is no point going faster than Gen1 for a x8 board.

Regards,
Eli

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by Guest »

Hi Eli,

Thanks for pointing out section 4.5 of the document. I will try it out.

May I know whether revB Xillybus FPGA bundles are also set as Gen1 (2.5GT/s) by default?

Thanks

Re: FPGA gives a "unknown header type 7f" with lspci command

Post by support »

Hello,

First of all, it's not clear why you want to configure the PCIe block above Gen1. If you're using a demo bundle with the board it's intended for, that will not improve your bandwidth.

But since you have done that -- did you follow section 4.5 of the Getting started with the FPGA demo bundle for Xilinx?

http://xillybus.com/downloads/doc/xilly ... xilinx.pdf

Changing the attributes of the PCIe block may require additional steps on some FPGA targets, or the PCIe interface becomes unstable.

Regards,
Eli

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