by support »
Hello,
This isn't really a question on Xillybus, but rather on general timing constraining. So I suggest referring to Xilinx' documentation and forums.
Anyhow, take a look on the timing report. I believe that you'll find that the 125 MHz is already constrained, as it's derived from the 250 MHz clock by a PLL. The tools usually automatically add a timing constraint in that case.
Then you might need to declare that the two clocks should be treated as unrelated ("asynchronous"). There is a special timing constraint for that (set_clock_groups -asynchronous). But in your special case of a 1:2 ratio, it might not make a big difference. In particular, if the PLL is set to align its output (125 MHz) with the input clock (250 MHz), the paths between these two clock domains won't cause any trouble, even in the absence of a set_clock_groups constraint. And it's safer that way (in case you accidentally generate some logic that crosses clock domains without due protection).
Regards,
Eli
Hello,
This isn't really a question on Xillybus, but rather on general timing constraining. So I suggest referring to Xilinx' documentation and forums.
Anyhow, take a look on the timing report. I believe that you'll find that the 125 MHz is already constrained, as it's derived from the 250 MHz clock by a PLL. The tools usually automatically add a timing constraint in that case.
Then you might need to declare that the two clocks should be treated as unrelated ("asynchronous"). There is a special timing constraint for that (set_clock_groups -asynchronous). But in your special case of a 1:2 ratio, it might not make a big difference. In particular, if the PLL is set to align its output (125 MHz) with the input clock (250 MHz), the paths between these two clock domains won't cause any trouble, even in the absence of a set_clock_groups constraint. And it's safer that way (in case you accidentally generate some logic that crosses clock domains without due protection).
Regards,
Eli