by support »
Hello,
A: "7M" simply means 7 million. 7 million accesses of 32 bit (= 4 bytes) is simply 4 x 7 = 28 MB/s. That's all.
A: The number 4096 is the size of the region to mmap. It should match (actually, not be larger than) the allocated section allocated by the hardware peripheral.
A: It might be desired to attach more than one than one Xillybus Lite unit on the FPGA side. In that case, another device tree entry is made for it, which causes Linux to generate another /dev/uioN file (i.e. /dev/uio1).
A: "Lite" means that this isn't the fullblown Xillybus IP core, which is DMA based, much faster and can work over a PCIe bus as well. Xillybus Lite is lightweight, slow and relatively CPU demanding when used heavily, and is intended primarily for setting registers of hardware etc.
Regards,
Eli
Hello,
A: "7M" simply means 7 million. 7 million accesses of 32 bit (= 4 bytes) is simply 4 x 7 = 28 MB/s. That's all.
A: The number 4096 is the size of the region to mmap. It should match (actually, not be larger than) the allocated section allocated by the hardware peripheral.
A: It might be desired to attach more than one than one Xillybus Lite unit on the FPGA side. In that case, another device tree entry is made for it, which causes Linux to generate another /dev/uioN file (i.e. /dev/uio1).
A: "Lite" means that this isn't the fullblown Xillybus IP core, which is DMA based, much faster and can work over a PCIe bus as well. Xillybus Lite is lightweight, slow and relatively CPU demanding when used heavily, and is intended primarily for setting registers of hardware etc.
Regards,
Eli