The Xillybus Forum

Hello,

Vivado 2017.3 seems to have silently dropped a feature on Xilinx' PCIe Gen3 block (Config External Interface), which isn't used by Xillybus. However this feature was enabled in the PCIe block's configuration, and Vivado just disabled it as the block was upgraded automatically. As a result, Vivado 2017.3 removed some of the PCIe block's ports. One of the missing ports is the one it complains about in the error message you attached.

This issue has been fixed recently. Please re-download an updated bundle from the website. All bundles with -2.0c (and later) suffixes should do the trick.

Regards,
Eli

Hi,

I'm new to FPGA and have no experience of HDL. I'm trying the bundle demo for Xilinx KCU105 Board with Vivado 2017.3.

I'm following the Xillybus demo guide with using blockdesign. The "Generate Bitstream" shows the following error:

ERROR: [Synth 8-448] named port connection 'cfg_ext_read_data' does not exist for instance 'pcie' of module 'pcie_ku' [/home/x29yan/workspace/fpga/xillybus/xillybus-eval-kintexultrascale-2.0a/blockdesign/blockdesign/ipshared/46fa/src/xillybus_block.v:421]
ERROR: [Synth 8-448] named port connection 'cfg_ext_read_data_valid' does not exist for instance 'pcie' of module 'pcie_ku' [/home/x29yan/workspace/fpga/xillybus/xillybus-eval-kintexultrascale-2.0a/blockdesign/blockdesign/ipshared/46fa/src/xillybus_block.v:422]