by Guest »
hello
we have been using Xillybus with VC707 board for a long time.
now we are trying to use Xillybus on a custom board having Virtex7 690 FPGA.
the port locations of GT lines and the reference clock are the same as VC707 board.
we downloaded demo bundle for VC709 board and generated a custom core from IP core factory for our custom board.
for core bundle we used "xillydemo-vivado.tcl" tcl command to generate a design.
After the design is generated we copied the files related to Xillybus to a new project.
In the new project we changed the
xillybus.v
xillybus_core.ngc
xillybus_core.v
files with the ones generated at IP core factory.
we modified the location of PCIE_PERST_B_LS port in xillydemo.xdc file with respect to our custom board.
when we run synthesis we get the errors related to port connections of pcie_v7_8x module below
.cfg_mgmt_addr(19'd0),
.cfg_mgmt_write(1'b0),
.cfg_mgmt_write_data(32'd0),
.cfg_mgmt_byte_enable(4'd0),
.cfg_mgmt_read(1'b0),
.cfg_mgmt_type1_cfg_reg_access(1'b0),
.cfg_msg_transmit(1'b0),
.cfg_msg_transmit_type(3'd0),
.cfg_msg_transmit_data(32'd0),c
.cfg_per_func_status_control(3'd0),
.cfg_ext_read_data(32'd0),
.cfg_ext_read_data_valid(1'b1),
since these ports are not activated in demo bundle we get errors.
therefore we comment out these lines and run synthesis and implementation again.
this time we do not get any error.
after the FPGA of custom board is programmed with the .bit file and the PC connected to Xillybus is reseted, the host PC does not recognize Xillybus in device manager.
When we examine the RX and TX line with scope we observe that while the signals driven by FPGA are not static the signals driven by PC are static.
what is our misteke?
do we need to make any changes to PCIe IP or Xillybus files?
Xillybus for Gen3 PCIe runs at 2.5GT/s. Do we have to connect our custom board with Virtex 7 690 to a Gen3 PCIe slot?
hello
we have been using Xillybus with VC707 board for a long time.
now we are trying to use Xillybus on a custom board having Virtex7 690 FPGA.
the port locations of GT lines and the reference clock are the same as VC707 board.
we downloaded demo bundle for VC709 board and generated a custom core from IP core factory for our custom board.
for core bundle we used "xillydemo-vivado.tcl" tcl command to generate a design.
After the design is generated we copied the files related to Xillybus to a new project.
In the new project we changed the
xillybus.v
xillybus_core.ngc
xillybus_core.v
files with the ones generated at IP core factory.
we modified the location of PCIE_PERST_B_LS port in xillydemo.xdc file with respect to our custom board.
when we run synthesis we get the errors related to port connections of pcie_v7_8x module below
.cfg_mgmt_addr(19'd0),
.cfg_mgmt_write(1'b0),
.cfg_mgmt_write_data(32'd0),
.cfg_mgmt_byte_enable(4'd0),
.cfg_mgmt_read(1'b0),
.cfg_mgmt_type1_cfg_reg_access(1'b0),
.cfg_msg_transmit(1'b0),
.cfg_msg_transmit_type(3'd0),
.cfg_msg_transmit_data(32'd0),c
.cfg_per_func_status_control(3'd0),
.cfg_ext_read_data(32'd0),
.cfg_ext_read_data_valid(1'b1),
since these ports are not activated in demo bundle we get errors.
therefore we comment out these lines and run synthesis and implementation again.
this time we do not get any error.
after the FPGA of custom board is programmed with the .bit file and the PC connected to Xillybus is reseted, the host PC does not recognize Xillybus in device manager.
When we examine the RX and TX line with scope we observe that while the signals driven by FPGA are not static the signals driven by PC are static.
what is our misteke?
do we need to make any changes to PCIe IP or Xillybus files?
Xillybus for Gen3 PCIe runs at 2.5GT/s. Do we have to connect our custom board with Virtex 7 690 to a Gen3 PCIe slot?