by Guest »
Hi, dear support,
I'm using Vivado HLS for design and employ the demo bundle project for baseline. I have a problem about the interface between the module generated by Vivado HLS and Xillybus IP, Xillybus-Lite IP.
In the following example, you demonstrate to use the "#pragma AP interface ap_fifo " and connect to Xillybus IP.
http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-2However, in the following document, you use "#pragma AP interface axis " on page 22 for the same example.
"The guide to Xillybus Block Design Flow for non-HDL users"
Would you please clarify which Vivado HLS interface types are suggested for Xillybus IP and Xillybus-Lite IP separately which Vivado HLS user can follow your guideline to generate proper interface to integrate with either Xillybus IP or Xillybus-Lite IP in their project ? Thanks
Hi, dear support,
I'm using Vivado HLS for design and employ the demo bundle project for baseline. I have a problem about the interface between the module generated by Vivado HLS and Xillybus IP, Xillybus-Lite IP.
In the following example, you demonstrate to use the "#pragma AP interface ap_fifo " and connect to Xillybus IP.
http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-2
However, in the following document, you use "#pragma AP interface axis " on page 22 for the same example.
"The guide to Xillybus Block Design Flow for non-HDL users"
Would you please clarify which Vivado HLS interface types are suggested for Xillybus IP and Xillybus-Lite IP separately which Vivado HLS user can follow your guideline to generate proper interface to integrate with either Xillybus IP or Xillybus-Lite IP in their project ? Thanks