Failed loop back test

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Re: Failed loop back test

Post by support »

Hello,

Indeed, there's no fork() in Windows. The example is intended to demonstrate the programming techniques, not necessarily fit any scenario perfectly.

In this matter, do what works best for you: You may want to split the program into two separate ones, and run them together. Or use multithreading. Or use command-line utilities.

Regards,
Eli

Re: Failed loop back test

Post by Guest »

Hi, Eli

Thanks for your kindly help and support.

Can "practical.c" run on windows 7 ?

fork() seems not to support windows, how can I do?

Thanks,
James

Re: Failed loop back test

Post by support »

Hello,

I can't tell what you've done from your description. The example you pointed at sends one data elements and then reads one element. How did you reach 1024 values? I suppose you looped. How you did that extension is probably where the problem lies.

But never mind that. There's a big yellow box saying "IMPORTANT", telling you not to use that code as an example, and refers to section 6.7 for something to actually work with. The differences between simple.c and practical.c are exactly the things that make something work accurately or not.

How about trying again, with practical.c as an example?

Alternatively, you may loop back with just "cat" or "dd", if you're on a Linux machine.

Regards,
Eli

Re: Failed loop back test

Post by Guest »

Hi, Eli

I mean I want to transfer the file(1024 data, each data 32bit).
I'm using blockdesign to do loop back test.
And then I found 1~50 data loop back can get the same value.
51~1024 data loop back get different value.
I think data loop back must be the same.

http://xillybus.com/downloads/doc/xillybus_block_design_flow.pdf
modify by P.25 <6.6 simple.c: An example of a host program>

Thanks,
James

Re: Failed loop back test

Post by support »

Hello,

It's not clear what went wrong. What do you mean with "front data loop back"? What front? What's the other loopback?

In short, what have you done, what did work and what didn't?

Regards,
Eli

Failed loop back test

Post by Guest »

Hello,

I'm new to FPGA. I'm trying the bundle demo for Xilinx VC709 Board with Vivado 2017.2 on Windows7.

I'm following the Xillybus demo guide with using blockdesign.
I am using stream read and write to transfer files(32bit) from host PC, process in the FPGA and send the data back (just loop back test).
I found the front data loop back can get the same value. But the other data loop back cause different value.

I need to guarantee data from host to FPGA can always be correct.
How can I do?

Greatly appreciate for any help in advance!

Thanks,
James

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