by helmutforren »
(Eli),
I don't have access to hardware or Xillybus yet, but I need to plan.
I'm anticipating a 32-bit wide architecture inside my FPGA. I'd like to interface with Xillybus using 32-bit wide FIFOs. Then, I guess, on the Linux side, the named pipes will be character devices that read/write 8 bits at a time, presumably in groups of 4 to get up to 32 bits.
Here are my questions.
1) Will the above paragraph work? That is, can I make the Xillybus FIFOs 32-bits wide?
2) Can somebody else on my FPGA use a different FIFO width?
3) Those serial ports of mine on Rx might receive a number of chars not a multiple of 4. This brings up a flushing and valid byte issue. Does Xillybus already have a solution for this issue?
4) Alternatively, could I make these Xillybus FIFOs 8-bits wide (mixing width where some are 8-bits, others are 32-its)?
5) Can
Thanks very much
Helmut
(Eli),
I don't have access to hardware or Xillybus yet, but I need to plan.
I'm anticipating a 32-bit wide architecture inside my FPGA. I'd like to interface with Xillybus using 32-bit wide FIFOs. Then, I guess, on the Linux side, the named pipes will be character devices that read/write 8 bits at a time, presumably in groups of 4 to get up to 32 bits.
Here are my questions.
1) Will the above paragraph work? That is, can I make the Xillybus FIFOs 32-bits wide?
2) Can somebody else on my FPGA use a different FIFO width?
3) Those serial ports of mine on Rx might receive a number of chars not a multiple of 4. This brings up a flushing and valid byte issue. Does Xillybus already have a solution for this issue?
4) Alternatively, could I make these Xillybus FIFOs 8-bits wide (mixing width where some are 8-bits, others are 32-its)?
5) Can
Thanks very much
Helmut