by Guest »
Eli,
Oh, wow, an answer already. I asked around, I forget, 3am my EDT.
Anyway, I'd like to pursue temporary holding of host reset or permanent modification of the FPGA board. I didn't design the FPGA board, or the third party host board, but I do have decades of EE experience. I just don't have specific knowledge about the resets of which we speak...
QUESTION ONE: In order to hold the host in reset, can that be done THROUGH the PCIe/104 connector? If so, would that be akin to the KC705 signal PCIE_PERST? Or is there a different signal to use while going through the PCIe/104 connector? (In the PCI104_Express_v3_0 spec I find only this same signal, called PERST#. I don't find any other reset. On the KC705 schematic, while there is a bidirectional buffer between PCIE_PERST and the FPGA, it's forced in the to-FPGA direction by wiring the 2DIR pin to ground. So I don't think the KC705 is designed to be able to hold the host in reset via this signal.)
QUESTION TWO: If bypassing the PCIe/104 connector with a separate wire, we do have debug outputs and test points available on the FPGA board. I could search for a place directly on the host to connect a wire, but I'll first ask if you have a recommendation...
QUESTION THREE: Aside from holding the host in reset, I could just work on configuring the FPGA ever faster. To date it's been using SPIx1 and either default clock (unknown, is it 3MHz?) or 3MHz. Faster clocks have been tested sporadically and not consistently enough. The circuit also works at SPIx2. DO YOU BELIEVE that pursuing this route might provide temporary relief, until perhaps a test mod and subsequent board respin could be done?
Thanks again,
Helmut
Eli,
Oh, wow, an answer already. I asked around, I forget, 3am my EDT.
Anyway, I'd like to pursue temporary holding of host reset or permanent modification of the FPGA board. I didn't design the FPGA board, or the third party host board, but I do have decades of EE experience. I just don't have specific knowledge about the resets of which we speak...
QUESTION ONE: In order to hold the host in reset, can that be done THROUGH the PCIe/104 connector? If so, would that be akin to the KC705 signal PCIE_PERST? Or is there a different signal to use while going through the PCIe/104 connector? (In the PCI104_Express_v3_0 spec I find only this same signal, called PERST#. I don't find any other reset. On the KC705 schematic, while there is a bidirectional buffer between PCIE_PERST and the FPGA, it's forced in the to-FPGA direction by wiring the 2DIR pin to ground. So I don't think the KC705 is designed to be able to hold the host in reset via this signal.)
QUESTION TWO: If bypassing the PCIe/104 connector with a separate wire, we do have debug outputs and test points available on the FPGA board. I could search for a place directly on the host to connect a wire, but I'll first ask if you have a recommendation...
QUESTION THREE: Aside from holding the host in reset, I could just work on configuring the FPGA ever faster. To date it's been using SPIx1 and either default clock (unknown, is it 3MHz?) or 3MHz. Faster clocks have been tested sporadically and not consistently enough. The circuit also works at SPIx2. DO YOU BELIEVE that pursuing this route might provide temporary relief, until perhaps a test mod and subsequent board respin could be done?
Thanks again,
Helmut