Look for suggestion on the use of Xillybus IP

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Expand view Topic review: Look for suggestion on the use of Xillybus IP

Re: Look for suggestion on the use of Xillybus IP

Post by Guest » Wed Sep 19, 2018 12:42 pm

Hi, support,

Thanks for the comment and I can realize that Xillubus IP doesn't cover DMA aspect like this use case.

All the best.

Re: Look for suggestion on the use of Xillybus IP

Post by support » Wed Sep 19, 2018 11:12 am


If the data in question is handled serially by the logic (i.e. it can be read from a FIFO), you might use a Xillybus stream to push the data from the host towards the PL as needed. Or use the Xillybus stream to write into the BRAMs occasionally. This means that the data is stored in some RAM memory array of the computer program, and it writes the data to the Xillybus device file in the way and order that it needs to be processed by the logic. If there are results to be fetched, read data from another Xillybus stream.

This may not appear to be the prettiest solution, but it's often the easiest way out.

A more intuitive solution is the one you suggested: Giving the logic in the PL a segment in the host's DRAM memory, and let it mind its own business. This requires more effort, of course, but in some scenarios there is no choice. You might design an AXI master for interfacing with one of the Zynq's HP slave ports, or you may use a DMA IP core supplied by Xilinx.

This way or another, this topic isn't specific to Xillybus: It's about how to utilize DMA traffic on a Zynq processor. I therefore suggest turning to Xilinx' support and forums for getting help on this.


Look for suggestion on the use of Xillybus IP

Post by Guest » Wed Sep 19, 2018 10:07 am

Hi, dear support,

I encountered a problem while porting Xillinux over ZYBO FPGA. The customized IP we developed has integrated into the Xilinux over ZYBO and works fine. Also, the IP utilizes some BRAMs in FPGA which the ARM9 can read or write the BRAM before enabling the IP. However, there is a spec run change of the IP which means to increase the size of the BRAM used by the IP. After the run change, the BRAMs are not enough and therefore we come up with to place the data in DRAM first by CPU and then use DMA to move the data into the local buffer inside the IP to resolve the issue. It turns out to need to change the design against the previous way. What I planned to modify is as follows :

1.Change to add the interface of the IP with one extra DMA interface
2.The DMA interface can access DRAM and write to internal SRAM of the IP

My question is : for such kind of spec over Xilinux (We'd like to leverage Xilinux again), I need your guidance to provide me some references on this which I can refer to change the RTL design accordingly. Thanks