by support »
Hello,
If the data in question is handled serially by the logic (i.e. it can be read from a FIFO), you might use a Xillybus stream to push the data from the host towards the PL as needed. Or use the Xillybus stream to write into the BRAMs occasionally. This means that the data is stored in some RAM memory array of the computer program, and it writes the data to the Xillybus device file in the way and order that it needs to be processed by the logic. If there are results to be fetched, read data from another Xillybus stream.
This may not appear to be the prettiest solution, but it's often the easiest way out.
A more intuitive solution is the one you suggested: Giving the logic in the PL a segment in the host's DRAM memory, and let it mind its own business. This requires more effort, of course, but in some scenarios there is no choice. You might design an AXI master for interfacing with one of the Zynq's HP slave ports, or you may use a DMA IP core supplied by Xilinx.
This way or another, this topic isn't specific to Xillybus: It's about how to utilize DMA traffic on a Zynq processor. I therefore suggest turning to Xilinx' support and forums for getting help on this.
Regards,
Eli
Hello,
If the data in question is handled serially by the logic (i.e. it can be read from a FIFO), you might use a Xillybus stream to push the data from the host towards the PL as needed. Or use the Xillybus stream to write into the BRAMs occasionally. This means that the data is stored in some RAM memory array of the computer program, and it writes the data to the Xillybus device file in the way and order that it needs to be processed by the logic. If there are results to be fetched, read data from another Xillybus stream.
This may not appear to be the prettiest solution, but it's often the easiest way out.
A more intuitive solution is the one you suggested: Giving the logic in the PL a segment in the host's DRAM memory, and let it mind its own business. This requires more effort, of course, but in some scenarios there is no choice. You might design an AXI master for interfacing with one of the Zynq's HP slave ports, or you may use a DMA IP core supplied by Xilinx.
This way or another, this topic isn't specific to Xillybus: It's about how to utilize DMA traffic on a Zynq processor. I therefore suggest turning to Xilinx' support and forums for getting help on this.
Regards,
Eli