Integrating xilly bus with custom IP

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Re: Integrating xilly bus with custom IP

Post by support » Thu Jul 02, 2020 9:07 am

Hello,

There is nothing in the code you wrote that would cause the error you reported. It's more likely to be a result of something else you did while attempting to integrate your own code into the project.

However I see no interaction with Xillybus' IP core here, making this issue non-Xillybus specific (?). If this is indeed the case, I suggest seeking help in Xilinx' forums.

Regards,
Eli

Integrating xilly bus with custom IP

Post by Guest » Thu Jul 02, 2020 8:56 am

Hello All,
I am trying to integrate the custom logic with xillybus host interface .First i have compiled default xilly bus demo bundle successfully bit file generated
but when i tried to integrate my own designed IP at host interface of xillybus it shows ERROR in Implementation as given below.
Again if i have delete my IP from current project the project show still same Errors.
can any one face similar error ? How an I do that?
MY IP CODE:
module wrapper(
input [0:31] data_in_TDATA,
input data_in_TVALID,
input data_in_TREADY,
input apclk,
input ap_rst_n,
output data_out_TREADY,
output reg data_out_TVALID,
output reg [0:31] data_out_TDATA
);



always @(posedge apclk)
begin
if ((data_out_TREADY==1) & (data_out_TREADY==1)) begin
if(data_in_TVALID==1'b1)
begin
data_out_TDATA<=data_in_TDATA+100;
data_out_TVALID<=1'b1;
end
else
begin
data_out_TVALID<=1'b0;
data_out_TDATA<=data_out_TDATA;
end
end
end
endmodule




Error:
[DRC INBB-3] Black Box Instances: Cell 'vivado_system_ins/xillyvga_0/inst/xillyvga_core_ins/vga_fifo_wrapper_ins/vga_fifo' of type 'vga_fifo' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

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