Using user_mem_8_addr_w with 32bit width?

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Expand view Topic review: Using user_mem_8_addr_w with 32bit width?

Re: Using user_mem_8_addr_w with 32bit width?

Post by support » Wed Aug 19, 2020 7:10 am

Hello,

Please follow the instructions. Since you want a 32 bit space instead of 8 bits, the module will have one port (the address port) slightly wider. So some slight modifications are necessary.

But after replacing the files as instructed, the compilation from is the same.

Regards,
Eli

Re: Using user_mem_8_addr_w with 32bit width?

Post by Guest » Wed Aug 19, 2020 7:01 am

Hi,

Thank you for all the help, also will the xillybus_core be recompiled differently if I use the IP core configurator?

Thanks.

Re: Using user_mem_8_addr_w with 32bit width?

Post by support » Wed Aug 19, 2020 6:57 am

Hello,

It was actually me getting a bit confused with the 32-bit thing, but the answer remains the same: Get your custom IP core at the IP Core Factory, and reading the docs is always a good idea...

Regards,
Eli

Re: Using user_mem_8_addr_w with 32bit width?

Post by Guest » Wed Aug 19, 2020 6:53 am

Hi,

I think I didn't clarify correctly. I want to still use the 8bit variant of a seekable stream but noticed the address is set to 5 bits everywhere, rather I want to increase address size and still access 8bits at a time. Can this only be done with the 32bit variant?

Cheers.

Re: Using user_mem_8_addr_w with 32bit width?

Post by support » Wed Aug 19, 2020 6:20 am

Hello,

Yes, please go to the IP Core Factory at the website and create a core that fits your needs.

Also please pay attention to section 6.1 in Xillybus host application programming guide for Linux / Windows ("Seekable Streams") which outlines how to work correctly with a 32-bit array. In particular, note that the you'll need to multiply the address set with lseek() by 4, since you're jumping four bytes for each element in the array.

Regards,
Eli

Using user_mem_8_addr_w with 32bit width?

Post by Guest » Tue Aug 18, 2020 10:50 pm

Hi,

I'm trying to compile the Intel FPGA demo with user_mem_8_addr set to be 32-bit wide rather than 5-bit. But I noticed it's locked to 5-bits by the xillybus_core module. Is there anyway to increase this?

Thanks.

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