PCIe driver couldn't be installed

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Expand view Topic review: PCIe driver couldn't be installed

Re: PCIe driver couldn't be installed

Post by mim » Fri Jan 01, 2021 9:03 am

support wrote:Hello,

I supposed you've followed section 4.5 "Getting started with the FPGA demo bundle for Xilinx"...?

http://xillybus.com/downloads/doc/xilly ... xilinx.pdf

In particular, in section 4.5.2, it says:

"After making the desired changes, verify that the Vendor and Device IDs haven’t changed (neither the Subsystem counterparts). Some revisions of Vivado may reset some parameters to their defaults as a result of unrelated modifications".

Have you indeed verified that?

Regards,
Eli




Dear Eli,
Thank you. To let you know: it fixed the problem; I should change Device ID into EBEB. The driver has been installed successfully.

Now I have another issue:
http://www.forum.xillybus.com/viewtopic.php?f=4&t=716

Re: PCIe driver couldn't be installed

Post by support » Mon Dec 28, 2020 4:04 pm

Hello,

I supposed you've followed section 4.5 "Getting started with the FPGA demo bundle for Xilinx"...?

http://xillybus.com/downloads/doc/xilly ... xilinx.pdf

In particular, in section 4.5.2, it says:

"After making the desired changes, verify that the Vendor and Device IDs haven’t changed (neither the Subsystem counterparts). Some revisions of Vivado may reset some parameters to their defaults as a result of unrelated modifications".

Have you indeed verified that?

Regards,
Eli

PCIe driver couldn't be installed

Post by Guest » Mon Dec 28, 2020 3:17 pm

Hello Xillybus team,

Thank you for sharing useful contents inside your website.
I have a x4 pcie xilinx board, and I tried to use your IP core and driver to maintain a streaming pcie communication between windows and FPGA board, however when I brows the address of xillybus-windriver-1.2.0.0 folder, unfortunately it couldn't be recognized by the windows. while I checked this with Jungo windriver, the coniguration space containing one BAR was recognized by the software, alongside this, the link up flag went high correctly.

What I have changed from your project are just related to the lane number (x8 to x4). when creating VHDL based project, I found thatthere is a module (xillybus_core.v) which is empty. In addition, I tried to create a block design based project, it couldn't be built due to this file (NGC).
Is it something related to this?

I would appreciate if you help me to fix this issue.

Regards
Mim

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