Unspecified IOSTANDARD on PCIE pins

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Expand view Topic review: Unspecified IOSTANDARD on PCIE pins

Re: Unspecified IOSTANDARD on PCIE pins

Post by support » Wed Sep 01, 2021 1:29 pm

Hello,

Actually, it's recommended to compare the XCI files with a diff tool if you make any changes from the original. There are a lot of parameters in those PCIe blocks.

And hopefully needless to say, you should copy the PCIe block from an XL demo bundle, and not the one available for download at the site (which is revA, and hence works only with revA and revB cores).

Regards,
Eli

Re: Unspecified IOSTANDARD on PCIE pins

Post by Guest » Wed Sep 01, 2021 1:24 pm

Ah, I see. All of the TX channels except for TX_0 were listed. I opened up the PCI endpoint IP and when I ported over to the new design the IP was reset to default values or something. It was a x1 lane default configuration, and needs to be updated.

Re: Unspecified IOSTANDARD on PCIE pins

Post by support » Wed Sep 01, 2021 1:10 pm

Hello,

Clearly, if this error appeared after you moved the core into your own project, something went wrong. So just ignoring it is probably a bad idea.

The fact that the PCIe pins aren't assigned with an I/O standard is weird in particular. Maybe you didn't connect them properly in the HDL project?

Regards,
Eli

Unspecified IOSTANDARD on PCIE pins

Post by Guest » Wed Sep 01, 2021 12:51 pm

Hello,

I am trying to add the XL core to an already existing custom logic project. During the generate bitstream stage, I get the following errors:

[DRC NSTD-1] Unspecified I/O Standard: 14 out of 320 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: PCIE_TX_N[7], PCIE_TX_N[6], PCIE_TX_N[5], PCIE_TX_N[4], PCIE_TX_N[3], PCIE_TX_N[2], PCIE_TX_N[1], PCIE_TX_P[7], PCIE_TX_P[6], PCIE_TX_P[5], PCIE_TX_P[4], PCIE_TX_P[3], PCIE_TX_P[2], and PCIE_TX_P[1].

[DRC UCIO-1] Unconstrained Logical Port: 14 out of 320 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: PCIE_TX_N[7], PCIE_TX_N[6], PCIE_TX_N[5], PCIE_TX_N[4], PCIE_TX_N[3], PCIE_TX_N[2], PCIE_TX_N[1], PCIE_TX_P[7], PCIE_TX_P[6], PCIE_TX_P[5], PCIE_TX_P[4], PCIE_TX_P[3], PCIE_TX_P[2], and PCIE_TX_P[1].


Can I safely run this tcl command and ignore these errors?

Thank you

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