The Xillybus Forum

Hello,

There's no connection between the widths of the streams (what you refer to as FIFOs) and the width of the interface with the PCIe block (128 bits in the case of an XL core). Configure the streams in the way that works best with your application logic.

For example, it's perfectly fine to choose 256 bits even though the interface with PCIe block is narrower. Xillybus utilizes the PCIe transport wisely to push data as quickly as possible, given the possibilities. You won't be able to push data at 256 bits x the clock rate in the situation, but it will still work in a sensible way.

Regards,
Eli

Hi,

I was following the xillycapture example in the FPGA designer guide document and noticed that the FIFOs in the demo bundle are still the default widths of 32bits and 8 bits while I have modified the bundle to the XL core with read widths of 128bits and write widths of 32bits.

Doing the speed test in the "Getting started with windows host" I have reached my desired speed and I am aware that there are a lot of intricacies on the back end so I was wondering if I should modify the FIFOs to match my read/write widths?

Thanks!