by support »
Hello,
There's no connection between the widths of the streams (what you refer to as FIFOs) and the width of the interface with the PCIe block (128 bits in the case of an XL core). Configure the streams in the way that works best with your application logic.
For example, it's perfectly fine to choose 256 bits even though the interface with PCIe block is narrower. Xillybus utilizes the PCIe transport wisely to push data as quickly as possible, given the possibilities. You won't be able to push data at 256 bits x the clock rate in the situation, but it will still work in a sensible way.
Regards,
Eli
Hello,
There's no connection between the widths of the streams (what you refer to as FIFOs) and the width of the interface with the PCIe block (128 bits in the case of an XL core). Configure the streams in the way that works best with your application logic.
For example, it's perfectly fine to choose 256 bits even though the interface with PCIe block is narrower. Xillybus utilizes the PCIe transport wisely to push data as quickly as possible, given the possibilities. You won't be able to push data at 256 bits x the clock rate in the situation, but it will still work in a sensible way.
Regards,
Eli