Talking about PCIe and Xillybus
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by support »
by mjuzwiak »
$ dd if=/dev/zero of=/dev/xillybus_write_test bs=16kB count=64kB64000+0 records in64000+0 records out1024000000 bytes (1.0 GB) copied, 13.5872 s, 75.4 MB/s
------- /dev/xillybus_read_test Upstream (FPGA to host): Data width: 32 bits DMA buffers: 32 x 128 kB = 4 MB Flow control: Asynchronous, select() and non-blocking read() supported Seekable: No------- /dev/xillybus_write_test Downstream (host to FPGA): Data width: 32 bits DMA buffers: 32 x 128 kB = 4 MB Flow control: Asynchronous Seekable: No FPGA RAM for DMA acceleration: 4 segments x 512 bytes = 2 kB------- /dev/xillybus_read_8 Upstream (FPGA to host): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Asynchronous, select() and non-blocking read() supported Seekable: No------- /dev/xillybus_write_8 Downstream (host to FPGA): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Asynchronous Seekable: No FPGA RAM for DMA acceleration: None------- /dev/xillybus_mem_8 Upstream (FPGA to host): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Synchronous Seekable: Yes, with 5 address bits Downstream (host to FPGA): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Synchronous Seekable: Yes, with 5 address bits FPGA RAM for DMA acceleration: None
by Guest »
INST "*/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X0Y2;NET "PCIE_REFCLK_P" LOC = "AF4" ;NET "PCIE_REFCLK_N" LOC = "AF3" ;NET "PCIE_PERST_B_LS" LOC = "AC24" ;
NET PCIE_CLK_QO_N LOC="AF3"; # Bank 118, MGTREFCLKN_118, GTP_DUAL_X0Y1NET PCIE_CLK_QO_P LOC="AF4"; # Bank 118, MGTREFCLKP_118, GTP_DUAL_X0Y1
$ dd if=file of=/dev/xillybus_write_322097152+0 records in2097152+0 records out1073741824 bytes (1.1 GB) copied, 12.2857 s, 87.4 MB/s
$ dd if=/dev/zero of=/dev/xillybus_write_32 bs=16k count=100KB100000+0 records in100000+0 records out1638400000 bytes (1.6 GB) copied, 18.2155 s, 89.9 MB/s
2048000+0 records in2048000+0 records out1048576000 bytes (1.0 GB) copied, 11.7009 s, 89.6 MB/s
2048000+0 records in2048000+0 records out1048576000 bytes (1.0 GB) copied, 11.8763 s, 88.3 MB/s
data sent - time - bandwidth64MB - 121ms : 528MB/s128MB - 776ms : 167MB/s256MB - 2310ms : 110MB/s512MB - 5396ms : 94MB/s1024MB - 11525ms : 89MB/s2048MB - 23851ms: 85MB/s4096MB - 48497ms: 84MB/s
------- /dev/xillybus_read_32 or \\.\xillybus_read_32 Upstream (FPGA to host): Data width: 32 bits DMA buffers: 64 x 1 MB = 64 MB Flow control: Asynchronous, select() and non-blocking read() supported (on Linux) Seekable: No------- /dev/xillybus_write_32 or \\.\xillybus_write_32 Downstream (host to FPGA): Data width: 32 bits DMA buffers: 64 x 1 MB = 64 MB Flow control: Asynchronous Seekable: No FPGA RAM for DMA acceleration: 8 segments x 512 bytes = 4 kB------- /dev/xillybus_read_8 or \\.\xillybus_read_8 Upstream (FPGA to host): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Asynchronous, select() and non-blocking read() supported (on Linux) Seekable: No------- /dev/xillybus_write_8 or \\.\xillybus_write_8 Downstream (host to FPGA): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Asynchronous Seekable: No FPGA RAM for DMA acceleration: None------- /dev/xillybus_mem_8 or \\.\xillybus_mem_8 Upstream (FPGA to host): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Synchronous Seekable: Yes, with 5 address bits Downstream (host to FPGA): Data width: 8 bits DMA buffers: 4 x 4 kB = 16 kB Flow control: Synchronous Seekable: Yes, with 5 address bits FPGA RAM for DMA acceleration: None
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