by support »
Hi,
I took a look on the xillybus.v file you sent me. There is indeed nothing special about it. Your pinout also seems OK.
Large DMA buffers can't reduce bandwidth, and in fact there is nothing, except synchronous streams, that can explain that bandwidth. Really.
I would also be quite surprised if it turned out to be a poor PCIe link. But I would make a quick try on another computer, if that is possible for you. Even though I wouldn't put my money on that this is the issue.
In all previous cases I had of this kind of black magic, it turned out that there was some confusion with old and new files. So to be absolutely sure that there really is a problem, please try this. Even though it appears like you've been through this already:
(1) Please create a new custom core for Virtex-5, based upon the default configuration. Change nothing except for the name of xillybus_write_32, to something else, say xillybus_write_test.
(2) Then adopt the downloaded core into a freshly downloaded demo project (replace the files), and adjust it: Rewire the full signal as you previously did, and search-replace write_32 to write_test.
(3) Adjust the UCF file
(4) Implement the project and load it to the FPGA
(5) Run the dd test you did above.
The idea behind this checkup is that we'll be absolutely sure that what is loaded into the FPGA is what we think it was. Otherwise, we start to suspect the hardware. So the next step is to try using another FPGA board and/or computer.
Regards,
Eli
Hi,
I took a look on the xillybus.v file you sent me. There is indeed nothing special about it. Your pinout also seems OK.
Large DMA buffers can't reduce bandwidth, and in fact there is nothing, except synchronous streams, that can explain that bandwidth. Really.
I would also be quite surprised if it turned out to be a poor PCIe link. But I would make a quick try on another computer, if that is possible for you. Even though I wouldn't put my money on that this is the issue.
In all previous cases I had of this kind of black magic, it turned out that there was some confusion with old and new files. So to be absolutely sure that there really is a problem, please try this. Even though it appears like you've been through this already:
(1) Please create a new custom core for Virtex-5, based upon the default configuration. Change nothing except for the name of xillybus_write_32, to something else, say xillybus_write_test.
(2) Then adopt the downloaded core into a freshly downloaded demo project (replace the files), and adjust it: Rewire the full signal as you previously did, and search-replace write_32 to write_test.
(3) Adjust the UCF file
(4) Implement the project and load it to the FPGA
(5) Run the dd test you did above.
The idea behind this checkup is that we'll be absolutely sure that what is loaded into the FPGA is what we think it was. Otherwise, we start to suspect the hardware. So the next step is to try using another FPGA board and/or computer.
Regards,
Eli