The Xillybus Forum

Hello,

For controlling the IP core's behavior, please create your custom IP core here:

http://xillybus.com/custom-ip-factory

If you'll play around with it a bit, I suppose things will clear up. But I realize now that there's place for confusion in that guide. I'll fix that.

And thanks for the P.S. :)

Regards,
Eli

Hello,

I am working with Xillybus now and reading the host programming guide, when I see the sync vs. async streaming part. I couldn't understand how async streaming works in Xillybus.

[quote]Each Xillybus stream has a flag, which determines whether it behaves synchronously
or asynchronously. This flag’s value is fixed in the FPGA’s logic.
For custom IP cores, the setting of this flag for each stream is stated in the “readme”
file included in the bundle. This flag is set automatically when the “Autoset internal”
option is used in the web tool, which is the recommended practice.
[/quote]

I am using the Altera Cyclone IV Core in Verilog. Where is the flag? and what is "Autoset internal"? I couldn't find any explanations in the docs. Can you point me to the right direction?

P.S. The docs for Xillybus is really great and complete. This is probably the only thing I couldn't find in it, but generally I am really fascinated by its quality. Great job.

Thanks,
M.P.