The Xillybus Forum

Hello,

To get an idea of the performance, you first need to untie to loopback in xillydemo, so that there's no link between the data sent to the FPGA and the one that arrives. In fact, it's enough just to make sure that the "empty" and "full" signals that are connected to the loopback FIFO are held zero. It's quite difficult to set up a performance test with data looping back, because the data flow gets stalled all the time.

You may write your own test application, or use the "dd" Linux command. Please note that the block size matters, as this has an influence on the operating system's overhead. Also please note that the write_8/read_8 pair isn't intended for heavy data transmission, and has a quite lousy performance. Go for write_32 and read_32, possibly with a custom IP core which has these configured for data acquisition / playback.

So it's basically something like

dd if=/dev/zero of=/dev/xillybus_write_32 bs=16k

and press CTRL-C after a few seconds. Possibly play with the "bs" parameter a bit. For this to work, the "full" signal on the FPGA must be held zero, which isn't the situation in the demo bundle as it arrives (which is why xillydemo.v/.vhd needs to be edited as mentioned above).

Regards,
Eli

Hi
thanks..

can we know the performance of PCIe utilized to transfer data in the demo apps for virtex 6?

Hi,

apna wrote:i want to edit the streamwrite program to write data from a file to console instead of writing directly to console ,what changes need to be made to the streamwrite program to attain this.

Why don't you just use streamread? It does exactly that: Reads from a file, outputs to stdout.

Regards,
Eli

Hi

As I edited xillydemo.v,the problem was solved ...thanks

i want to edit the streamwrite program to write data from a file to console instead of writing directly to console ,what changes need to be made to the streamwrite program to attain this.

thank you.

Hello,

Please refer to the README.TXT file that is included in the custom IP core bundle. In particular this item in the instructions:

(3) Edit xillydemo.v (or xillydemo.vhd) to reflect the desired application
of this custom IP core. The template.v (or template.vhd) file in the
"instantiation templates" directory of this bundle contains the signal
outline and instantion format.

It looks like you didn't edit your Xillydemo file correctly or at all.

Regards,
Eli

Hi..

I had generated the ip core according to my requirements and followed the steps in the "xillybus_getting_started_xilinx.pdf",but as i started the "Generate Programming File” to implement, i got the following errors...


Elaborating module <xillybus_core>.
WARNING:HDLCompiler:1499 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillybus_core.v" Line 1: Empty module <xillybus_core> remains a black box.
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 63: Cannot find port user_r_mem_8_rden on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 64: Cannot find port user_r_mem_8_empty on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 65: Cannot find port user_r_mem_8_data on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 66: Cannot find port user_r_mem_8_eof on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 67: Cannot find port user_r_mem_8_open on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 70: Cannot find port user_w_mem_8_wren on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 71: Cannot find port user_w_mem_8_full on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 72: Cannot find port user_w_mem_8_data on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 73: Cannot find port user_w_mem_8_open on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 76: Cannot find port user_mem_8_addr on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 77: Cannot find port user_mem_8_addr_update on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 82: Cannot find port user_r_read_32_rden on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 83: Cannot find port user_r_read_32_empty on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 84: Cannot find port user_r_read_32_data on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 85: Cannot find port user_r_read_32_eof on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 86: Cannot find port user_r_read_32_open on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 90: Cannot find port user_w_write_32_wren on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 91: Cannot find port user_w_write_32_full on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 92: Cannot find port user_w_write_32_data on this module
Sorry, too many errors..
WARNING:HDLCompiler:1499 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 1: Empty module <xillydemo> remains a black box.


what could be the reason for this ? i have copied all the newly generated files to the demo bundle.

thanks.

Hello,

Please generate your custom IP core in the IP Core Factory: http://xillybus.com/custom-ip-factory

Also, please refer to the getting started and programming guides for more information about how to interact with the device files. It's all down to basic reading and writing to files.

Regards,
Eli

Hi

I need larger buffer(512-1024),does the demoapp provide any program,for large buffers?

hows the execution of the fifo program given in the demo bundle?

thanks...

Hello,

Unless you need really huge buffers (>512MB or so), I don't think you really need to use that utility.

Anyhow, it's not clear exactly what you did, so I can't help you much as is.

Regards,
Eli

thank you eli....

I reprogrammed the FPGA and loaded the driver. Now its working well.

As i tried to execute the FIFO program ,i got the message as

"./fifo 3
0 bytes in FIFO, 0 read, 0 written"