by support »
Hello,
32 bit width is indeed the correct choice for best throughput.
As for DMA buffers -- Xillybus maintains a set of DMA buffers which are used for the data transport. There's most likely no point to dive into the details of the underlying mechanism, as it's designed to make optimal use of the bandwidth when it's under heavy load, and being slightly inefficient under lighter load.
So from a user's point of view, just try to send as much data as you have. If you have a 1 MB buffer in user space, call write() with the entire buffer. If the return value indicates that not all was written, re-issue write() calls until it's completely written. Xillybus takes care of the optimizations.
As for synchronous vs. asynchronous streams -- this issue is discussed in the documentation, but to put it short: The only thing it determines, is if data can run across the FPGA and host between read() and write() calls, like "in the background". When the streams are used just to shuffle data, asynchronous streams are the preferred choice, but when they're used to communicate commands and status information, synchronous streams are necessary, as it matters when the data was read and when it arrived.
I hope this put things clearer.
Regards,
Eli
Hello,
32 bit width is indeed the correct choice for best throughput.
As for DMA buffers -- Xillybus maintains a set of DMA buffers which are used for the data transport. There's most likely no point to dive into the details of the underlying mechanism, as it's designed to make optimal use of the bandwidth when it's under heavy load, and being slightly inefficient under lighter load.
So from a user's point of view, just try to send as much data as you have. If you have a 1 MB buffer in user space, call write() with the entire buffer. If the return value indicates that not all was written, re-issue write() calls until it's completely written. Xillybus takes care of the optimizations.
As for synchronous vs. asynchronous streams -- this issue is discussed in the documentation, but to put it short: The only thing it determines, is if data can run across the FPGA and host between read() and write() calls, like "in the background". When the streams are used just to shuffle data, asynchronous streams are the preferred choice, but when they're used to communicate commands and status information, synchronous streams are necessary, as it matters [b]when[/b] the data was read and when it arrived.
I hope this put things clearer.
Regards,
Eli