by support »
Hello,
Not meeting timing is often a fundamental design issue -- often a change in the design itself is required to fix it. The common term for fixing a problem like this is "timing closure". Xilinx has a lot of documentation on this topic. It has nothing to do with Xillybus specifically.
One thing to note is that Xillybus' user interface clock, bus_clk, runs at 250 MHz on Virtex-7 Xillybus bundles, which is quite high. Since the connection with Xillybus' IP core goes through FIFOs, it's possible to use dual-clock ("asynchronous") FIFOs, and run the application logic with any clock of choice. If the 250 MHz clock is an issue, this can help.
Regards,
Eli
Hello,
Not meeting timing is often a fundamental design issue -- often a change in the design itself is required to fix it. The common term for fixing a problem like this is "timing closure". Xilinx has a lot of documentation on this topic. It has nothing to do with Xillybus specifically.
One thing to note is that Xillybus' user interface clock, bus_clk, runs at 250 MHz on Virtex-7 Xillybus bundles, which is quite high. Since the connection with Xillybus' IP core goes through FIFOs, it's possible to use dual-clock ("asynchronous") FIFOs, and run the application logic with any clock of choice. If the 250 MHz clock is an issue, this can help.
Regards,
Eli