by danielyxie »
Hi Eli,
This seems to have done the trick, it looks as if flushing is working properly and does not post any errors. Thanks for the help!
However, we have run into another issue. Would you mind offering any guidance on that?
We are generating a 144-byte packet on a host computer and sending 100 copies of this packet through Xillybus to a Virtex-7 FPGA. For some reason, only 36 of these packets are received by the FIFO on the FPGA, which we have verified using a debug core and a packet capture device. So 64 packets are being dropped somewhere before the FIFO and we are unsure where or why. Also, when sending 100 packets, the number of packets that are successfully transmitted is always 36.
The code for this consists of a for loop that executes 100 times:
- Code: Select all
for(i = 0; i < 100; i ++) {
sendUDPPacket(data, 90, sourceip, destip, destPort);
}
where the sendUDPPacket() function consists of a single write() call.
Hi Eli,
This seems to have done the trick, it looks as if flushing is working properly and does not post any errors. Thanks for the help!
However, we have run into another issue. Would you mind offering any guidance on that?
We are generating a 144-byte packet on a host computer and sending 100 copies of this packet through Xillybus to a Virtex-7 FPGA. For some reason, only 36 of these packets are received by the FIFO on the FPGA, which we have verified using a debug core and a packet capture device. So 64 packets are being dropped somewhere before the FIFO and we are unsure where or why. Also, when sending 100 packets, the number of packets that are successfully transmitted is always 36.
The code for this consists of a for loop that executes 100 times:
[code]
for(i = 0; i < 100; i ++) {
sendUDPPacket(data, 90, sourceip, destip, destPort);
}[/code]
where the sendUDPPacket() function consists of a single write() call.