The Xillybus Forum

Hello,

Yes, Xillybus offers seekable streams, which have address lines on the FPGA side. These can be seamlessly connected to synchronous RAMs on the FPGA, or to anything that emulates a synchronous RAM -- in particular a register/data interface with wr_en, rd_en address, data and clock.

Please refer to the examples for memread and memwrite in the documentation. The FPGA demo bundle includes such a memory interface already (xillybus_mem_8).

Regards,
Eli

Hi Eli and all,
Is it possible to create a software accessible register using Xillybus? I am successfully transferring data from my C++ program to a FIFO using the respective device file's name /dev/xillybus/write_32. In a similar manner, could I use Xillybus to pass an integer variable in my C++ program to a register in my verilog code? If this is possible, what changes would need to be made in verilog code associated with the Xillybus demo bundle that I am using? Thank you very much