by support »
Hello,
In principle, there is no limit. In practice, the limit is dictated by the amount of logic that the FPGA can take (usually there's also application logic that does something with the data) and meeting timing constraints: The multiplexing elements in the IP core get larger, and therefore slower, as the number of streams rises. This is relevant in particular on FPGAs with a bus_clk of 250 MHz.
Actual tests have been done with around 60 streams on SP605 (Spartan-6 LX45T) for example. But it's possible to go higher if required on larger devices.
Regards,
Eli
Hello,
In principle, there is no limit. In practice, the limit is dictated by the amount of logic that the FPGA can take (usually there's also application logic that does something with the data) and meeting timing constraints: The multiplexing elements in the IP core get larger, and therefore slower, as the number of streams rises. This is relevant in particular on FPGAs with a bus_clk of 250 MHz.
Actual tests have been done with around 60 streams on SP605 (Spartan-6 LX45T) for example. But it's possible to go higher if required on larger devices.
Regards,
Eli