The Xillybus Forum

Hello,

Planahead isn't supported. However if you managed to get a design that meets timing constraints, why don't you try it out?

The said warning seems to be related to the line in the UCF file saying

[code]AREA_GROUP "area_xillybus" RANGE="SLICE_X166Y52:SLICE_X217Y149";[/code]

The purpose of this line is to keep the IP core's logic at a certain physical region on the FPGA, as it turned out that the placer spreads it out too much otherwise, and then failing to meet timing. So if you have no timing issues, you may remove this line altogether.

Regards,
Eli

Hi Eli and all,

I would like to use Xillybus in PlanAhead, so I have included everything (hdl files, netlist ngc file, ucf file and pcie files). And I use Xilinx Virtex-707 for my design and have set up the configuration in Project Settings properly.

However there is no error, but I've got a warning message:

[b]Unrecognized symbol SLICE_X166Y52 ["xillybus_vc707.ucf"][/b]

Is there any idea why such thing happened? Or am I missing something?

Thanks a lot for help, and best regards.