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Hello,
The Xillybus IP core binary targets an entire FPGA family, rather than a single device, so any core for Virtex 5 is fine. Please refer to section 4.3.3 in the Getting started with the FPGA demo bundle for Xilinx (available at the Documentation section) for how to build the design correctly.
As for using an ISE version different than ISE 13.1, section 4.3.3 also suggests how to get around that. You'll still have to install ISE 13.1 on your system (there is no need for additional licensing from Xilinx), but you'll be able to implement your design on your version of choice.
Regards,
Eli
Hello,
The Xillybus IP core binary targets an entire FPGA family, rather than a single device, so any core for Virtex 5 is fine. Please refer to section 4.3.3 in the Getting started with the FPGA demo bundle for Xilinx (available at the Documentation section) for how to build the design correctly.
As for using an ISE version different than ISE 13.1, section 4.3.3 also suggests how to get around that. You'll still have to install ISE 13.1 on your system (there is no need for additional licensing from Xilinx), but you'll be able to implement your design on your version of choice.
Regards,
Eli