by mohdamir »
Yup, I've already tied *_eof to 0 in my FPGA. This is what I have done, by modifying/adding the code in VHDL (as shown below).
*Note 1: in my HLS code, I removed debug header *.h and also I removed the code of debug, and I didn't change anything for the rest of the sample code. Furthermore, I used Virtex 707 and my clock period is 4 ns (without uncertainty).
*Note 2: I tried to use 10 ns for the clock period in HLS, however there are always timing error (at least 4 timing not met), so I changed to 4 ns, and made a little tweak in placer cost table such that all timing are met.
This is what I have done for my FPGA:
1) adding wires/registers
- Code: Select all
// Wires related to HLS_wrapper
wire [31:0] in_r_dout;
wire in_r_read;
wire hls_fifo_rd_en;
reg in_r_empty_n;
wire [31:0] out_r_din;
wire out_r_full;
wire out_r_write;
2) adding FIFO (to function) with Xillybus/HLS
- Code: Select all
fifo_32x512 fifo_to_function
(
.clk(bus_clk),
.srst(!user_w_write_32_open),
.din(user_w_write_32_data),
.wr_en(user_w_write_32_wren),
.rd_en(hls_fifo_rd_en),
.dout(in_r_dout),
.full(user_w_write_32_full),
.empty(hls_fifo_empty) );
assign hls_fifo_rd_en = !hls_fifo_empty && (in_r_read || !in_r_empty_n);
always @(posedge bus_clk)
if (!user_w_write_32_open) in_r_empty_n <= 0;
else if (hls_fifo_rd_en) in_r_empty_n <= 1;
else if (in_r_read) in_r_empty_n <= 0;
3) adding FIFO (from_function)
- Code: Select all
fifo_32x512 fifo_from_function
(
.clk(bus_clk),
.srst(!user_r_read_32_open),
.din(out_r_din),
.wr_en(out_r_write),
.rd_en(user_r_read_32_rden),
.dout(user_r_read_32_data),
.full(out_r_full),
.empty(user_r_read_32_empty) );
assign user_r_read_32_eof = 0;
4) adding wrapper for hls_wrapper
- Code: Select all
xillybus_wrapper HLS_wrapper
(
.ap_clk(bus_clk),
.ap_rst(!user_w_write_32_open || !user_r_read_32_open),
.in_r_dout(in_r_dout),
.in_r_empty_n(in_r_empty_n),
.in_r_read(in_r_read),
.out_r_din(out_r_din),
.out_r_full_n(!out_r_full),
.out_r_write(out_r_write) );
Yup, I've already tied *_eof to 0 in my FPGA. This is what I have done, by modifying/adding the code in VHDL (as shown below).
*Note 1: in my HLS code, I removed debug header *.h and also I removed the code of debug, and I didn't change anything for the rest of the sample code. Furthermore, I used Virtex 707 and my clock period is 4 ns (without uncertainty).
*Note 2: I tried to use 10 ns for the clock period in HLS, however there are always timing error (at least 4 timing not met), so I changed to 4 ns, and made a little tweak in placer cost table such that all timing are met.
This is what I have done for my FPGA:
1) adding wires/registers
[code]// Wires related to HLS_wrapper
wire [31:0] in_r_dout;
wire in_r_read;
wire hls_fifo_rd_en;
reg in_r_empty_n;
wire [31:0] out_r_din;
wire out_r_full;
wire out_r_write;[/code]
2) adding FIFO (to function) with Xillybus/HLS
[code] fifo_32x512 fifo_to_function
(
.clk(bus_clk),
.srst(!user_w_write_32_open),
.din(user_w_write_32_data),
.wr_en(user_w_write_32_wren),
.rd_en(hls_fifo_rd_en),
.dout(in_r_dout),
.full(user_w_write_32_full),
.empty(hls_fifo_empty) );
assign hls_fifo_rd_en = !hls_fifo_empty && (in_r_read || !in_r_empty_n);
always @(posedge bus_clk)
if (!user_w_write_32_open) in_r_empty_n <= 0;
else if (hls_fifo_rd_en) in_r_empty_n <= 1;
else if (in_r_read) in_r_empty_n <= 0; [/code]
3) adding FIFO (from_function)
[code] fifo_32x512 fifo_from_function
(
.clk(bus_clk),
.srst(!user_r_read_32_open),
.din(out_r_din),
.wr_en(out_r_write),
.rd_en(user_r_read_32_rden),
.dout(user_r_read_32_data),
.full(out_r_full),
.empty(user_r_read_32_empty) );
assign user_r_read_32_eof = 0;[/code]
4) adding wrapper for hls_wrapper
[code] xillybus_wrapper HLS_wrapper
(
.ap_clk(bus_clk),
.ap_rst(!user_w_write_32_open || !user_r_read_32_open),
.in_r_dout(in_r_dout),
.in_r_empty_n(in_r_empty_n),
.in_r_read(in_r_read),
.out_r_din(out_r_din),
.out_r_full_n(!out_r_full),
.out_r_write(out_r_write) );[/code]