The Xillybus Forum

Hello,

This is somewhat off-topic (this forum is about Xillybus, not tweaking Xillinux), but I can suggest three ways of doing this:

(1) Attach Xilinx' UART or UART lite core to the processor's AXI bus, and modify the device tree so the kernel detects them. You might also need to recompile the FSBL so the processor is configured correctly.
(2) Connect 8-bit Xillybus streams to Xilinx' UART cores, after hacking the logic, so they get their data from a dedicated FIFO and not through the AXI bus.
(3) Wire the processor's hardware UART's to EMIO, and connect the PMOD pins to these. This requires making changes in the device tree, and definitely requires recompiling the FSBL.

Depending on your personal preference, you can pick either.

I suggest reading my comments in these two threads, in particular on how to reconstruct the boot.bin file:

http://forum.xillybus.com/viewtopic.php?f=4&t=319
http://forum.xillybus.com/viewtopic.php?f=4&t=329

Regards,
Eli

Hello.

I am developing a project in which I want to use a UART interface to receive data from a Bluetooth receiver, using two Pmod GPIO on a ZYBO running Xillinux. I have checked the tutorials for reading/writing on the FIFOs and some tutorials on how to use /sys/class/gpio to use the GPIOs, but I'm not sure of what I must do to get a UART communication going with a Xillinux app.

Could you kindly give me some help with this?

Thanks!