by Guest »
Hi, eli,
Your first solution works very well. I just tried, now the whole system works perfectly except that the channel sequence change from [ch0,ch1,ch2,...ch15] to [ch1,ch2,ch3,...ch15,ch0], each channel sample data is int32 now. Probably is the problem of FWFT-FIFO? But at least, the multichannel FIR filter works very well with two FIFO through AXI4 stream! The total quantization error between FPGA filter and MATLAB filter is less than 1e-5, but FPGA is massively parallel.
I have a further question. For my project, it is going to collect external data stream instead of downloading data from HOST to FPGA, and the external data stream is indeed 16 bits wide with multichannel interleaved. Do I need to change the first FIFO data width to 16bits-in and 16-bits out in that case?
Best,
Chongxi
Hi, eli,
Your first solution works very well. I just tried, now the whole system works perfectly except that the channel sequence change from [ch0,ch1,ch2,...ch15] to [ch1,ch2,ch3,...ch15,ch0], each channel sample data is int32 now. Probably is the problem of FWFT-FIFO? But at least, the multichannel FIR filter works very well with two FIFO through AXI4 stream! The total quantization error between FPGA filter and MATLAB filter is less than 1e-5, but FPGA is massively parallel.
I have a further question. For my project, it is going to collect external data stream instead of downloading data from HOST to FPGA, and the external data stream is indeed 16 bits wide with multichannel interleaved. Do I need to change the first FIFO data width to 16bits-in and 16-bits out in that case?
Best,
Chongxi