The Xillybus Forum

Hello,

Indeed, what you described is how the loopback works.

You can't use xillybus_pcie only, because it depends on xillybus_core. Accordingly, there will be no device files to access.

It looks like you want to write your own PCIe endpoint regardless of Xillybus. I don't think Xillybus is a good reference for that purpose, even though its simple use may make it look appealing. It's actually the other way around: Xillybus' design under the hood is quite complex in order to make the user experience simple. If you're making your own design, you probably want to make the design as simple as possible, at the expense of a less general-purpose user interface.

If that's indeed the case, I would warmly suggest trying to get help on Xilinx' forums, as you will get a wider response. This forum focuses on Xillybus and basic questions about PCIe.

Regards,
Eli

hello,
normally iam using pipes xillybus_write_8 & xillybus_read_8 to write and read data....its working absolutely good.....
This is loop back of hardware fifo on FPGA side correct...?
Process is like what i have write to xillybus_write_8 will be given as input to 8-bit fifo and what i have read from xillybus_read_8 id data out from that fifo...This is a loop back....u have done correct............??

What i want is i want to send and receive data through pcie port not through pipes created.....
1. What are device files created if i install xillybus_pcie.c (no xillybus_core.c)...............??
2. how can i access that files with demo apps............??

k sir tq..

Hello,

The entire mechanism for transporting data is somewhat complicated, and involves DMA and handshaking mechanisms between the FPGA and the host.

The data itself travels by virtue of TLP packets requesting reads and writes issued by the FPGA side.

Regards,
Eli

hello eli sir,
If iam sending data (to dev file xillybus_write_32) and getting the same data (from xillybus_read_32)..
So i want to know how the path data is travelling...
1. the data will be written to PCIe port / 32-bit fifo as input / to ram...........??
2. from where fifo output/ ram output / pcie port to xillybus_read_32 dev file data will come..???

Hello,

There is plenty of documentation on the site on how to interface with Xillybus' IP core.

http://xillybus.com/doc

Regards,
Eli

How would i know what is the operation done by that module....
Can u provide me a source for this module...

Hello,

xillybus_core.v is a "black box" module -- it's deliberately empty, and as such it tells the synthesizer that the actual logic will be added at a later stage of the implementation, by xillybus_core.ngc (or xillybus_core.edf on some targets).

It's a bit like a header file in C: It tells the synthesizer what the port interface is, but without the content.

Regards,
Eli

i am seeing the modules u have provided..
unfortunately xillybus_core.v module architecture was empty..
i found only ports of that module..

Actually what is that xillybus_core.v module for....??? in our demo bundle..